On improved graph-based alternative wiring scheme for multi-level logic optimization
作者： Y.-L. Wu , C.-N. Sze , C.-C. Cheung , H. Fan
DOI: 10.1109/ICECS.2000.912962
关键词: Integrated circuit layout 、 Algorithm 、 Logic optimization 、 Minification 、 Algebraic operation 、 Speedup 、 Logic gate 、 Mathematics 、 Electronic circuit 、 Automatic test pattern generation
摘要: A much extended graph-based alternative wiring (GBAW) scheme to identify wires in multilevel logic with promising results is presented. By modeling subsets of circuits as minimal graphs and applying purely local pattern search technique, we have found more than 40 graph patterns which contain within 2-edge distance from the target wire. Applying proper grouping technique for similar patterns, complexity our rewiring can be reduced. Experimental on MCNC benchmarks show that faster ATPG-based RAMBO competitive number found. With this augmented family wires, are able find 30% compared 75 times speedup average. We applied GBAW minimization a perturbation engine simplify circuit by SIS algebraic operations. Results further reduction 11.1% literal count operations alone.
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