Integrated Placement and Skew Optimization for Rotary Clocking

摘要: The clock distribution network is a key component on any synchronous VLSI design. As technology moves into the nanometer era, innovative clocking techniques are required to solve power dissipation and variability issues. Rotary novel technique which employs unterminated rings formed by differential transmission lines save reduce skew variability. Despite its appealing advantages, rotary requires latch locations match pre-designed rings. This requirement difficult chicken-and-egg problem prevents wide application. In this work, we proposed an integrated placement scheduling methodology break hurdle, making compatible with practical design flows. A flow based assignment algorithm cost-driven optimization developed. Experiments show that our method can generate chip placements satisfy unique requirements of clocks, without sacrificing quality. By enabling concurrent design, also be applied in other methodologies as well