Ispd2009 clock network synthesis contest

摘要: Clock network synthesis (CNS) is one of the most important design challenges in high performance synchronized VLSI designs. However, without appropriate problem examples and real-world objectives, research can become less relevant to industrial flows. To address need community, we organize a clock contest set benchmark suite released. Since full-specification physical electrical requirements leading-edge processor distribution would be cumbersome impractical for this contest, make formulation familiar academia; that synthesize, buffer, tune distribution. objective function has been modified appropriately include increasing importance robustness variation, addition typical power metrics. The paper briefly describes ISPD suite.