作者: Sachin S. Sapatnekar , Yaoguang Wei , Frank Liu , Jiang Hu
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摘要: At 65 nm and below, Rapid Thermal Annealing (RTA) makes a significant contribution to manufacturing process variations, degrading the parametric yield. RTA-induced variability strongly depends on circuit layout patterns, particularly distribution of density Shallow Trench Isolation (STI) regions. In this work, we investigate two-step approach reduce impact variations. We first solve floorplanning problem that aims RTA variations by evening out STI distribution. Next, insert dummy polysilicon fills further improve uniformity density. Experimental results show our floorplanner can global 39% local 29% average with low overhead compared traditional floorplanner, proposed fill algorithm negligible amounts. Moreover, when inserting fills, for layouts obtained average, 24% fewer are inserted, as from floorplanner.