引用次数
引用: 4,767
H-指数: 34
I10-指数 : 79
出版物: 136
LATCH: A Locality-Aware Taint CHecker
Daniel Townley , Khaled N. Khasawneh , Dmitry Ponomarev , Nael Abu-Ghazaleh
international symposium on microarchitecture 969 -982
1
2019
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks
Leonid Domnitser , Aamer Jaleel , Jason Loew , Nael Abu-Ghazaleh
high performance embedded architectures and compilers 8 ( 4) 35
263
2012
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose , Oguz Ergin
Power-Aware Computer Systems 15 -29
35
2005
Optimization of Parallel Discrete Event Simulator for Multi-core Systems
Deepak Jagtap , Nael Abu-Ghazaleh , Dmitry Ponomarev
international parallel and distributed processing symposium 520 -531
37
2012
EA-PLRU: Enclave-Aware Cache Replacement
Atsuko Shimizu , Daniel Townley , Mohit Joshi , Dmitry Ponomarev
hardware and architectural support for security and privacy 5
1
2019
Controlled Asynchronous GVT: Accelerating Parallel Discrete Event Simulation on Many-Core Clusters
Ali Eker , Barry Williams , Kenneth Chiu , Dmitry Ponomarev
international conference on parallel processing
3
2019
Characterizing and Understanding PDES Behavior on Tilera Architecture
Deepak Jagtap , Ketan Bahulkar , Dmitry Ponomarev , Nael Abu-Ghazaleh
workshop on parallel and distributed simulation 53 -62
16
2012
Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation
Ketan Bahulkar , Jingjing Wang , Nael Abu-Ghazaleh , Dmitry Ponomarev
workshop on parallel and distributed simulation 221 -230
12
2012
Performance Analysis of a Multithreaded PDES Simulator on Multicore Clusters
Jingjing Wang , Dmitry Ponomarev , Nael Abu-Ghazaleh
workshop on parallel and distributed simulation 93 -95
9
2012
SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors
Daniel Townley , Dmitry Ponomarev
international conference on parallel architectures and compilation techniques 43 -54
4
2019
A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks
Jesse Elwell , Ryan Riley , Nael Abu-Ghazaleh , Dmitry Ponomarev
high-performance computer architecture 201 -212
9
2014
Malware-aware processors: A framework for efficient online malware detection
Meltem Ozsoy , Caleb Donovick , Iakov Gorelik , Nael Abu-Ghazaleh
high-performance computer architecture 651 -661
86
2015
Rethinking Memory Permissions for Protection Against Cross-Layer Attacks
Jesse Elwell , Ryan Riley , Nael Abu-Ghazaleh , Dmitry Ponomarev
ACM Transactions on Architecture and Code Optimization 12 ( 4) 56
3
2015
Energy-Efficient Design of the Reorder Buffer
Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose ,
power and timing modeling optimization and simulation 289 -299
17
2002
An L2-miss-driven early register deallocation for SMT processors
Joseph Sharkey , Dmitry Ponomarev
international conference on supercomputing 138 -147
7
2007
Exploring many-core architecture design space for parallel discrete event simulation
Yi Zhang , Jingjing Wang , Dmitry Ponomarev , Nael Abu-Ghazaleh
principles of advanced discrete simulation 95 -104
2
2014
How the spectre and meltdown hacks really worked
Nael Abu-Ghazaleh , Dmitry Ponomarev , Dmitry Evtyushkin
IEEE Spectrum 56 ( 3) 42 -49
8
2019
Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures
Hui Zeng , Kanad Ghose , Dmitry Ponomarev
2009 International Conference on Parallel Processing 453 -461
2
2009
Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures
Jason Loew , Dmitry Ponomarev
international conference on parallel processing 182 -189
2
2008