作者: D. Deschacht
DOI: 10.1109/DTIS.2010.5487575
关键词: RC circuit 、 Network analysis 、 Inductance 、 Electronic engineering 、 Circuit performance 、 Interconnection 、 System on a chip 、 Signal integrity 、 Computer science 、 Very-large-scale integration
摘要: As the interconnect lines play an increasingly dominant role in determining circuit performance, dynamic delay variation due to switching activity of neighboring has be accurately characterized. The goal this work is simulate effect inductance and routing orientation then investigate their effects on timing performances by considering three configurations parallel coupled interconnects. For a Deep-Sub-Micron process, we show that when analyzing VLSI circuits, if standard distributed RC models are used, inductive ignored, large errors can occur prediction evaluation behaviour. Both affect greatly performances.