Inductance analysis of on-chip interconnects [deep submicron CMOS]
作者： S. Kundu , U. Ghoshal
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摘要: It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency circuits rises above GHz level. In this paper we show perception not true. necessary to consider inductive effects in all implemented deep submicron CMOS technologies. For 0.25 /spl mu/m (lithography) technologies, where supply voltage expected be range 1.2-1.8 V, are an consideration regardless system frequency. Furthermore, contrary popular belief even for highly resistive lines.
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