A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

作者: Arash Hejazi , SeongJin Oh , Muhammad Riaz Ur Rehman , Reza E. Rad , SungJin Kim

DOI: 10.1109/TIM.2020.2995249

关键词: Frequency multiplierElectronic engineeringTime-to-digital converterCharge pumpAmplitudeThroughput (business)Power (physics)Clock signalCommunication channelComputer science

摘要: This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through coarse counter, middle, fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle delay-locked loops (ADDLLs) is provided to ensure stability of generated slots. Charge pump, loop filter, voltage-controlled line inside conventional analog (DLLs) are replaced an accumulator (ACC) digitally controlled (DCDL). makes design particularly compact, low power, suitable applications. presented can generate information amplitude variation (walk error) compensation. measuring pulsewidth position three successive STOP pulses each channel within single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates 625-MHz internal clock signal out 25-MHz external reference oscillator, which shrinks number elements cover one period improves precision TDC. Operation at higher provides high throughput short conversion (less than 3 ns). three-level offers 13.1- $\mu \text{s}$ maximum input range 50-ps resolution. measured DNL INL circuit 0.47 0.71 LSB, respectively. implemented in 180-nm standard CMOS process with die size 1.5 mm $\times1.5$ mm. total power consumption 87.6 mW.

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