A fine time-resolution (≪ 3 ps-rms) time-to-digital converter for highly integrated designs
作者： Lukas Perktold , Jorgen Christiansen
DOI: 10.1109/I2MTC.2013.6555583
关键词: Electronic engineering 、 Voltage 、 Sensitivity (electronics) 、 Differential nonlinearity 、 Calibration 、 Time-to-digital converter 、 Interpolation 、 Mathematics 、 Resistive touchscreen 、 Least significant bit
摘要: A multi-channel 3-ps-rms single-shot precision timeto-digital converter (TDC) is presented. The time interpolation based on a delay-locked-loop (DLL) employing resistive to achieve least-significant-bit (LSB) sizes as small 5 ps. To calibrate out device mismatches, only the timing-reference signals need be calibrated. usual for calibrating each channel individually avoided. After calibration, measured differential-non-linearity (DNL) and integral-non-linearity (INL) are ±0.9 LSB ±1.3 respectively. prototype, implemented in commercial 130 nm technology, consumes between 34mW 42 mW/channel shows voltage sensitivity of -0.19 ps/mV temperature dependence 0.44 ps/°C. best our knowledge this first TDC demonstrates precisions multiple channels smaller than 3ps-rms.
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