作者: P. Keranen , K. Maatta , J. Kostamovaara
关键词: Time-to-digital converter 、 Engineering 、 Jitter 、 Electronic engineering 、 Control theory 、 Integral nonlinearity 、 Field-programmable gate array 、 Gate array 、 Phase noise 、 Noise (electronics) 、 Integrator
摘要: A high-resolution time-to-digital converter (TDC) was designed and tested. The is based on the fundamental method of counting full clock cycles a low-phase-noise reference using single-stage interpolating employing time-to-amplitude converters that are Miller integrators. Counters other control logic were implemented field-programmable gate array, interpolation units constructed discrete components. single-shot precision uncompensated about 1.8 ps over time interval range 0 to 328 μs. Single-shot limited by nonlinearities interpolators. These measurement errors caused systematic, thus, can be improved 1 simple integral nonlinearity compensation. Other important factors contribute N -cycle jitter noise generated TDC circuit itself. By careful design, these made small enough achieve picosecond-level precision.