A new delay line loops shrinking time-to-digital converter in low-cost FPGA
作者： Jie Zhang , Dongming Zhou
DOI: 10.1016/J.NIMA.2014.10.040
关键词: Process (computing) 、 Delay calculation 、 Time-to-digital converter 、 Physics 、 Field-programmable gate array 、 Electronic engineering 、 Line (text file) 、 Interval (mathematics) 、 Delay-locked loop 、 Delay line oscillator
摘要: Abstract The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method implemented in low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost flexibility is presented. two which are used to directly shrink measured time interval designed TDC, dependent difference between entire times loops. In order realize eliminate temperature influence, consist same cells number. delay-locked loop (DLL) stabilize against process variations ambient conditions. Meanwhile, one accurately evaluate TDC. has been general-propose FPGA device (Actel SmartFusion A2F200M3). single shot 63.3 ps measurement standard deviation about 61.7 ps within range 5 ns.
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