A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix.
作者： Min Zhang , Hai Wang , Yan Liu , None
DOI: 10.3390/S17040865
关键词:
摘要: In this paper, a high-resolution time-to-digital converter (TDC) based on field programmable gate array (FPGA) device is proposed and tested. During the implementation, new architecture of TDC which consists measurement matrix with 1024 units. The utilization routing resources as delay elements distinguishes design from other existing designs, contributes most to insensitivity variations temperature voltage. Experimental results suggest that resolution 7.4 ps, INL (integral nonlinearity) DNL (differential are 11.6 ps 5.5 indicates offers high performance among available TDCs. Benefitting FPGA platform, has superiorities in easy low cost, short development time.
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