A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS
作者： Jun-Seok Kim , Young-Hun Seo , Yunjae Suh , Hong-June Park , Jae-Yoon Sim
DOI: 10.1109/JSSC.2012.2217892
关键词:
摘要: This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An clocking scheme realizes operation for higher The TDC was standard 0.13-μm CMOS technology has maximum throughput of 300 MS/s resolution 1.76 ps total conversion range 1.8 ns. measured DNL INL were 0.6 LSB 1.9 LSB, respectively.
harvard.edu
postech.ac.kr参考文章(19)
Young-Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim, A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$ m CMOS IEEE Journal of Solid-state Circuits. ,vol. 47, pp. 736- 743 ,(2012) , 10.1109/JSSC.2011.2176609
P. Dudek, S. Szczepanski, J.V. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 240- 247 ,(2000) , 10.1109/4.823449
Khurram Waheed, Robert Bogdan Staszewski, Fikret Dulger, Mahbuba S. Ullah, Socrates D. Vamvakos, Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences IEEE Transactions on Circuits and Systems. ,vol. 58, pp. 2051- 2060 ,(2011) , 10.1109/TCSI.2011.2163981
B.K. Swann, B.J. Blalock, L.G. Clonts, D.M. Binkley, J.M. Rochelle, E. Breeding, K.M. Baldwin, A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications IEEE Journal of Solid-state Circuits. ,vol. 39, pp. 1839- 1852 ,(2004) , 10.1109/JSSC.2004.835832
Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao, A high-precision time-to-digital converter using a two-level conversion scheme ieee nuclear science symposium. ,vol. 51, pp. 1349- 1352 ,(2003) , 10.1109/TNS.2004.832902
B. Murmann, B.E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification international solid-state circuits conference. ,vol. 38, pp. 2040- 2050 ,(2003) , 10.1109/JSSC.2003.819167
Abdel S. Yousif, James W. Haslett, A Fine Resolution TDC Architecture for Next Generation PET Imaging IEEE Transactions on Nuclear Science. ,vol. 54, pp. 1574- 1582 ,(2007) , 10.1109/TNS.2007.903183
Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan, Debapriya Sahu, Khurram Waheed, John Wallberg, Robert Bogdan Staszewski, Quantization noise improvement of Time to Digital converter (TDC) for ADPLL international symposium on circuits and systems. pp. 1020- 1023 ,(2009) , 10.1109/ISCAS.2009.5117932
Jianjun Yu, Fa Foster Dai, Richard C. Jaeger, A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology IEEE Journal of Solid-state Circuits. ,vol. 45, pp. 830- 842 ,(2010) , 10.1109/JSSC.2010.2040306
Weitao Li, Fule Li, Chun Zhang, Zhihua Wang, A digital background calibration algorithm based on code occurrence count for pipelined ADCs international conference on communications, circuits and systems. pp. 550- 553 ,(2009) , 10.1109/ICCCAS.2009.5250472