An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space
作者： Yeomyung Kim , Tae Wook Kim
DOI: 10.1109/TCSI.2014.2304656
关键词:
摘要: This paper presents a fine-resolution time-to-digital converter (TDC) with large dynamic range using 3-D Vernier space. Despite the wide range, required delay cells in delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits redundancy and error-correction technique solve offset error of coarse conversion space architecture. is implemented 0.13- μm CMOS process. measurement result shows an 11-bit 6.98-ps resolution, integrated nonlinearity ±1.5 LSB, consumption 328.8 μW, die area 0.28 mm 2 .
elsevier.com
sci-hub.se 参考文章(32)
P.G.A. Jespers, B. Ginetti, A 1.5 Ms/s 8-Bit Pipelined RSD A/D Converter european solid-state circuits conference. ,vol. 1, pp. 137- 140 ,(1990)
Ying Cao, Wouter De Cock, Michiel Steyaert, Paul Leroux, 1-1-1 MASH $\Delta \Sigma$ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping IEEE Journal of Solid-state Circuits. ,vol. 47, pp. 2093- 2106 ,(2012) , 10.1109/JSSC.2012.2199530
Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello, A Dither-Less All Digital PLL for Cellular Transmitters IEEE Journal of Solid-state Circuits. ,vol. 47, pp. 1908- 1920 ,(2012) , 10.1109/JSSC.2012.2197130
B. Razavi, B.A. Wooley, A 12-b 5-Msample/s two-step CMOS A/D converter IEEE Journal of Solid-state Circuits. ,vol. 27, pp. 1667- 1678 ,(1992) , 10.1109/4.173092
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho, A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier IEEE Journal of Solid-state Circuits. ,vol. 48, pp. 1009- 1017 ,(2013) , 10.1109/JSSC.2013.2237996
Jianjun Yu, Fa Foster Dai, A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOS custom integrated circuits conference. pp. 1- 4 ,(2010) , 10.1109/CICC.2010.5617431
C. Niclass, A. Rochas, P.-A. Besse, E. Charbon, Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes IEEE Journal of Solid-state Circuits. ,vol. 40, pp. 1847- 1854 ,(2005) , 10.1109/JSSC.2005.848173
Jun-Seok Kim, Young-Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim, A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS IEEE Journal of Solid-state Circuits. ,vol. 48, pp. 516- 526 ,(2013) , 10.1109/JSSC.2012.2217892
Bojan Markovic, Simone Tisa, Federica A. Villa, Alberto Tosi, Franco Zappa, A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation IEEE Transactions on Circuits and Systems. ,vol. 60, pp. 557- 569 ,(2013) , 10.1109/TCSI.2012.2215737
Young-Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim, A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$ m CMOS IEEE Journal of Solid-state Circuits. ,vol. 47, pp. 736- 743 ,(2012) , 10.1109/JSSC.2011.2176609