摘要: This study provides an in-depth review of the principles, architectures and design techniques CMOS time-to-digital converters (TDCs). The classification TDCs is introduced. It followed by examination parameters quantifying performance TDCs. Sampling including direct-counter TDCs, tapped delay-line pulse-shrinking cyclic with interpolation, vernier flash successive approximation pipelined are studied their pros cons compared. Noise-shaping that reduce in-band noise below technology limit investigated. These include gated ring oscillator switched relaxation ΔΣ MASH sampling noise-shaping direction future research on explored.
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