Low power instruction fetch using profiled variable length instructions

摘要: Computer system performance depends on high access rate and low miss in the instruction cache, which also affects energy consumed by fetching instructions. Simulation of a small computer typical for embedded systems shows that up to 20% overall processor is fetch path as much 23% execution time spent fetch. Therefore it key importance reduce dissipated during One way increase memory bandwidth more instructions each without increasing bus width. We propose an extension RISC ISA, with variable length instructions, yielding higher information density compromising programmability. Based profiling dynamic usage argument locality set SPEC CPU2000 applications, we present scheme using 816- 24-bit accompanied lookup tables inside Our yields 20-30% reduction main usage, experiments show 60% all executed consist short The savings are 15% entire data system, path.