Executing compressed programs on an embedded RISC architecture

摘要: The difference in code size between RISC and CISC processors appears to be a significant factor limiting the use of architectures embedded systems. Fortunately, programs can effectively compressed. An ideal solution is design system that directly execute compressed programs. A new architecture called Compressed Code Processor presented. This processor depends on code-expanding instruction cache manage compression transparent since all instructions are executed from cache. Experimental simulations show degree achieved fixed encoding scheme. impact performance slight for some memory implementations reduced bandwidth actually increases performance.