作者: M. Dubois , C. Scheurich
DOI: 10.1109/32.55094
关键词: Memory management 、 Computer multitasking 、 Non-lock concurrency control 、 Computer science 、 Multiprocessing 、 Parallel computing 、 Concurrency 、 Shared memory 、 Multiversion concurrency control 、 CPU cache
摘要: The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. problem implementing given multiprocessor is addressed. Two models are considered, simple rules introduced verify that architecture adheres models. applied several examples architectures. >