12b 50MSample/s two-stage A/D converter

摘要: A 12 b 50 MSample/s two-stage A/D converter in a complementary bipolar process uses coarse and fine encoders based upon cascaded magnitude amplifier design. The ADC provides 80 dB SFDR for 20 Mz analog input at 50MSPS while dissipating only 575 mW. Compared to other pipeline ADCs, subranging flash architecture minimizes the number of digital delays, but requires large comparators converters implement high-resolution An eleven absolute value or amplifiers, referred as magamps, realize sub-ranging ADC. gain alignment subtraction DAC rely on statistical matching process, linearity is obtained without laser trim. fabricated high-speed dielectrically isolated that allows more than harmonic suppression up an frequency MHz keeping total power dissipation mW from single +5 V supply.