A 12 b 128 MSample/s ADC with 0.05 LSB DNL

摘要: This analog-to-digital converter uses integrated dither, dynamic element matching, and output data scrambling to achieve SFDR of 85dB DNL below 0.05LSB at l28MSample/s. compares about 0.5LSB for slower 12b converters. The basic two-step flash architecture is shown. /spl plusmn/0.25V input amplified plusmn/1V held in the track-and-hold circuit when clock rises. 32 comparators ADC1 produce an approximation that switches matched current sources main DAC. residue formed summer plusmn/0.5V converted by ADC2, 8b folding-and-interpolating ADC. To allow low rates, there no analog pipelining, all settling from track-to-hold transition latching result ADC2 takes only 4.4ns. results added together form output. total signal-to-data-output delay slightly more than two cycles due digital pipelining.