A 12-bit 100 MS / s pipelined ADC with digital background calibration
作者： Zhou Liren , Luo Lei , Ye Fan , Xu Jun , Ren Junyan
DOI: 10.1088/1674-4926/30/11/115007
关键词:
摘要: This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog (MDAC) while architecture of MDAC remains unchanged. When sampled at MS/s, it takes only 2.8 s to calibrate prototype ADC and achieves peak spurious-free dynamic range 85 dB signal-to-noise plus distortion ratio 66 2 MHz input. Integral nonlinearity improved from 1.9 0.6 least significant bits after The chip fabricated in 0.18 μm process, occupies an active area 2.3 × 1.6 mm2, consumes 205 mW 1.8 V.
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