A 12 bit 100 MS/s pipelined analog to digital converter without calibration

摘要: A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter (ADC) in a 0.18 μm complementary metal-oxide semiconductor process is presented. The first stage adopts 3.5 structure relax the capacitor matching requirements. bootstrapped switch and scaling down technique are used improve ADC's linearity save power dissipation, respectively. With 15.5 MHz input signal, ADC achieves 79.8 dB spurious-free dynamic range 10.5 effective number of bits at MS/s. consumption 112 mW supply, including output drivers. chip area 3.51 mm2, pads.