Background interstage gain calibration technique for pipelined ADCs
作者： J.P. Keane , P.J. Hurst , S.H. Lewis
关键词:
摘要: A background self-calibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline algorithmic analog-to-digital converters (ADCs). Stage redundancy a architecture exploited to measure gain are corrected using digital post-processing. The allows faster convergence has less dependence on input signal statistics than similar described by Murmann Boser. Simulation results presented for 12-bit pipelined ADC architecture, Boser, nonideal residue amplifiers. With calibration, simulations show signal-to-noise-and-distortion-ratio performance 72 dB spurious-free dynamic range 112 dB, with calibration tracking time constants approximately 8/spl times/10/sup 5/ sample periods, which over ten times reported Boser at level.
sci-hub.se 参考文章(20)
Jun Ming, S.H. Lewis, An 8b 80MSample/s pipelined ADC with background calibration international solid-state circuits conference. pp. 42- 43 ,(2000) , 10.1109/ISSCC.2000.839683
D. Kelly, W. Yang, I. Mehr, M. Sayuk, L. Singer, A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist international solid-state circuits conference. pp. 134- 135 ,(2001) , 10.1109/ISSCC.2001.912575
Rudy GH Eschauzier, Johan Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers ,(1995)
S.H. Lewis, P.R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter IEEE Journal of Solid-State Circuits. ,vol. 22, pp. 954- 961 ,(1987) , 10.1109/JSSC.1987.1052843
E.J. Siragusa, I. Galton, Gain error correction technique for pipelined analogue-to-digital converters Electronics Letters. ,vol. 36, pp. 617- 618 ,(2000) , 10.1049/EL:20000501
Y.-M. Lin, B. Kim, P.R. Gray, A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS IEEE Journal of Solid-state Circuits. ,vol. 26, pp. 628- 636 ,(1991) , 10.1109/4.75065
B. Murmann, B.E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification international solid-state circuits conference. ,vol. 38, pp. 2040- 2050 ,(2003) , 10.1109/JSSC.2003.819167
S.-U. Kwak, B.-S. Song, K. Bacrania, A 15 b 5 MSample/s low-spurious CMOS ADC international solid-state circuits conference. ,vol. 32, pp. 1866- 1875 ,(1997) , 10.1109/4.643645
C.R. Grace, P.J. Hurst, S.H. Lewis, A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration international solid-state circuits conference. ,vol. 40, pp. 1038- 1046 ,(2004) , 10.1109/JSSC.2005.845972
S.M. Jamal, Daihong Fu, N.C.-J. Chang, P.J. Hurst, S.H. Lewis, A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration international solid-state circuits conference. ,vol. 37, pp. 1618- 1627 ,(2002) , 10.1109/JSSC.2002.804327