A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS

摘要: Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and fewer clock cycles error averaging techniques. Since self-calibration can be performed during interframe intervals, this particularly attractive A 3- mu m CMOS prototype fabricated using architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, occupies 40 kmil/sup 2/ (26 mm/sup 2/), with single 5-V supply two-phase nonoverlapping clock. >