Method and direct memory access controller for asynchronously reading/writing data from/to a memory with improved throughput

摘要: Buffer lines and corresponding buffer tags valid/dirty registers in conjunction with control circuit are provided to a DMA controller enabling the conditionally pre-fetch data from memory while being read transferred I/O device during operations write back written operations, thereby improving asynchronous read/write throughputs. Read requests, random as well sequential, satisfied pre-fetched if they validly stored. Write deferred, batched optimized. The improved throughput is achieved manner completely transparent system software.