作者: Werner Grollitsch
DOI:
关键词: Line (electrical engineering) 、 Control theory 、 Clock skew 、 Shift register 、 Reset (computing) 、 Register (music) 、 Signal 、 Computer science 、 Electronic engineering 、 Delayed phase
摘要: An apparatus for the controlled delay of an input signal includes a receiving signal. The is supplied to line with multiplicity elements. Outputs elements allow respective differently delayed phase signals be tapped off. Furthermore, register provided. are each associated one Each has reset and clock input. inputs coupled outputs element therewith.