Clock generator circuit providing an output clock signal from phased input clock signals

摘要: A clock generator circuit accepts phased input signals having an frequency, and generates from the output signal low jitter a frequency created by dividing or multiplying frequency. In exemplary embodiments four duty cycle correction feature, provides frequencies of divided X/2, where X is integer. other not correction, X/4. The delay through minimal, independent divisor. Variations include programmable divisors multipliers optional phase shifting.