High-speed fault simulation for UNIVAC 1107 computer system

摘要: A high-speed logic simulation system of programs with the ability to simulate faults has been implemented for UNIVAC(R) 1107 Computer System. The central simulator program is capable achieving an average speed less than one-half microsecond per logical element and a capacity up 10,000 components, simulated memory 256 bytes. Among techniques employed achieve are (1) component “levelizing,” automatic equation ordering method, (2) compiler method evaluation, (3) parallel or simultaneous evaluations model, (4) storage model equations in main (5) fault simulation, perturbations.