Digital logic testing and simulation

摘要: Preface. 1 Introduction. 1.1 1.2 Quality. 1.3 The Test. 1.4 Design Process. 1.5 Automation. 1.6 Estimating Yield. 1.7 Measuring Test Effectiveness. 1.8 Economics of 1.9 Case Studies. 1.9.1 Effectiveness Fault Simulation. 1.9.2 Evaluating Decisions. 1.10 Summary. Problems. References. 2 2.1 2.2 Background. 2.3 Simulation Hierarchy. 2.4 Logic Symbols. 2.5 Sequential Circuit Behavior. 2.6 Compiled Simulator. 2.6.1 Ternary 2.6.2 2.6.3 Timing Considerations. 2.6.4 Hazards. 2.6.5 Hazard Detection. 2.7 Event-Driven 2.7.1 Zero-Delay 2.7.2 Unit-Delay 2.7.3 Nominal-Delay 2.8 Multiple-Valued 2.9 Implementing the 2.9.1 Scheduler. 2.9.2 Descriptor Cell. 2.9.3 Evaluation Techniques. 2.9.4 Race Detection in 2.9.5 Min-Max Timing. 2.10 Switch-Level 2.11 Binary Decision Diagrams. 2.11.1 2.11.2 Reduce Operation. 2.11.3 Apply 2.12 Cycle 2.13 Verification. 2.13.1 Path Enumeration. 2.13.2 Block-Oriented Analysis. 2.14 3 3.1 3.2 Approaches to Testing. 3.3 Analysis a Faulted Circuit. 3.3.1 at Component Level. 3.3.2 Gate-Level 3.3.3 Gate 3.4 Stuck-At Model. 3.4.1 AND 3.4.2 OR 3.4.3 Inverter 3.4.4 Tri-State 3.4.5 Equivalence and Dominance. 3.5 Simulator: An Overview. 3.6 Parallel Processing. 3.6.1 3.6.2 Performance Enhancements. 3.6.3 Pattern Single Propagation. 3.7 Concurrent 3.7.1 Example 3.7.2 Algorithm. 3.7.3 Simulation: Further 3.8 Delay 3.9 Differential 3.10 Deductive 3.11 Statistical 3.12 Performance. 3.13 4 Automatic Generation. 4.1 4.2 Sensitized Path. 4.2.1 Path: Example. 4.2.2 Method. 4.3 D-Algorithm. 4.3.1 D-Algorithm: 4.3.2 Primitive D-Cubes Failure. 4.3.3 Propagation D-Cubes. 4.3.4 Justification Implication. 4.3.5 D-Intersection. 4.4 Testdetect. 4.5 Subscripted 4.6 PODEM. 4.7 FAN. 4.8 Socrates. 4.9 Critical 4.10 Tracing. 4.11 Boolean Differences. 4.12 Satisfiability. 4.13 Using BDDs for ATPG. 4.13.1 BDD XOR 4.13.2 Faulting Graph. 4.14 5 5.1 5.2 Problems Caused by Logic. 5.2.1 Effects Memory. 5.2.2 5.3 Methods. 5.3.1 Seshu's Heuristics. 5.3.2 Iterative Generator. 5.3.3 9-Value ITG. 5.3.4 5.3.5 Extended Backtrace. 5.3.6 Sensitization. 5.4 Complexity. 5.4.1 Acyclic Circuits. 5.4.2 Balanced 5.4.3 General 5.5 Experiments with Machines. 5.6 A Theoretical Limit on Testability. 5.7 6 Equipment. 6.1 6.2 Basic Tester Architectures. 6.2.1 Static Tester. 6.2.2 Dynamic 6.3 Standard Interface Language. 6.4 6.5 Electron Beam Probe. 6.6 Manufacturing 6.7 Developing Board Strategy. 6.8 In-Circuit 6.9 PCB 6.9.1 Emulating 6.9.2 Reference 6.9.3 Diagnostic Tools. 6.10 Plan. 6.11 Visual Inspection. 6.12 Cost. 6.13 7 7.1 7.2 Triad. 7.3 Overview 7.4 Testbench. 7.4.1 Description. 7.4.2 Stimulus 7.5 Modeling. 7.5.1 Checkpoint Faults. 7.5.2 7.5.3 Redundant 7.5.4 Bridging 7.5.5 7.6 Technology-Related 7.6.1 MOS. 7.6.2 CMOS. 7.6.3 Coverage Results Equivalent 7.7 7.7.1 Random Patterns. 7.7.2 Seed Vectors. 7.7.3 Sampling. 7.7.4 Fault-List Partitioning. 7.7.5 Distributed 7.7.6 7.7.7 Incremental 7.7.8 Initialization. 7.7.9 Profiles. 7.7.10 Dictionaries. 7.7.11 Dropping. 7.8 Behavioral 7.8.1 MUX. 7.8.2 Algorithmic Development. 7.8.3 7.8.4 Toggle Coverage. 7.8.5 Code 7.9 7.9.1 Trapped 7.9.2 SOFTG. 7.9.3 Imply 7.9.4 Comprehension Versus Resolution. 7.9.5 Probable Detected 7.9.6 Compaction. 7.9.7 Counting. 7.10 Miscellaneous 7.10.1 ATPG/Fault Simulator Link. 7.10.2 ATPG User Controls. 7.10.3 Management. 7.11 8 Design-For-Testability. 8.1 8.2 Ad Hoc Design-for-Testability Rules. 8.2.1 Some Testability 8.2.2 Solutions. 8.3 Controllability/Observability 8.3.1 SCOAP. 8.3.2 Other Measures. 8.3.3 Measure 8.3.4 8.4 Scan 8.4.1 8.4.2 Types Scan-Flops. 8.4.3 Level-Sensitive Design. 8.4.4 Compliance. 8.4.5 Scan-Testing Circuits 8.4.6 8.5 Partial 8.6 Solutions PCBs. 8.6.1 NAND Tree. 8.6.2 1149.1 Boundary Scan. 8.7 9 Built-In Self-Test. 9.1 9.2 Benefits BIST. 9.3 Self-Test Paradigm. 9.3.1 Mathematical Basis 9.3.2 LFSR. 9.3.3 Multiple Input Signature Register (MISR). 9.3.4 BILBO. 9.4 9.4.1 Determining 9.4.2 9.4.3 Weighted 9.4.4 Aliasing. 9.4.5 BIST Results. 9.5 Applications. 9.5.1 Microprocessor-Based 9.5.2 MISR/Parallel SRSG (STUMPS). 9.5.3 STUMPS ES/9000 System. 9.5.4 S/390 Microprocessor. 9.5.5 Macrolan Chip. 9.5.6 9.6 Remote 9.6.1 Controller. 9.6.2 Desktop Management Interface. 9.7 Black-Box 9.7.1 Ordering Relation. 9.7.2 Microprocessor Matrix. 9.7.3 Graph 9.8 Tolerance. 9.8.1 Monitoring. 9.8.2 Self-Checking 9.8.3 Burst Error Correction. 9.8.4 Triple Modular Redundancy. 9.8.5 Software Implemented 9.9 10 Memory 10.1 10.2 Semiconductor Organization. 10.3 10.4 10.5 10.5.1 GALPAT Implementation. 10.5.2 9N 13N Algorithms. 10.5.3 10.5.4 Memories. 10.5.5 Weak Read-Write. 10.6 Repairable 10.7 Correcting Codes. 10.7.1 Vector Spaces. 10.7.2 Hamming 10.7.3 ECC 10.7.4 Reliability Improvements. 10.7.5 Iterated 10.8 11 IDDQ. 11.1 11.2 11.3 Selecting 11.3.1 Count. 11.3.2 Quietest 11.4 Choosing Threshold. 11.5 Current. 11.6 IDDQ Burn-In. Large 11.8 12 12.1 12.2 Verification: 12.3 12.3.1 12.3.2 HDL Extensions C++. 12.3.3 Co-design Co-verification. 12.4 Thoroughness. 12.4.1 Evaluation. 12.4.2 12.5 12.6 12.6.1 12.6.2 RTL Image. 12.6.3 Library Parameterized Modules. 12.6.4 Processing 12.7 Search System (SCIRTSS). 12.7.1 State Traversal Problem. 12.7.2 Petri Net. 12.8 Expert. 12.8.1 TDX. 12.8.2 DEPOT. 12.8.3 12.8.4 Building Goal Trees. 12.8.5 Conflicts 12.8.6 12.8.7 Bidirectional Search. 12.8.8 Constraint 12.8.9 Pitfalls When 12.8.10 MaxGoal MinGoal. 12.8.11 Functional Walk. 12.8.12 Learn Mode. 12.8.13 DFT 12.9 12.9.1 Formal 12.9.2 Theorem Proving. 12.9.3 Checking. 12.9.4 Model 12.9.5 Symbolic 12.10Summary. Index.