LOVERD--a logic design verification and diagnosis system via test generation

摘要: The development of cost-effective circuits is primarily a matter economy. To achieve it, design errors and circuit flaws must be eliminated during the process. this end, considerable effort put into all phases cycle. Effective CAD tools are essential for production high-performance digital systems. This thesis describes tool called LOVERD, which consists ATPG, fault simulation, verification diagnosis. It uses test patterns, developed to detect single stuck-at faults in gate-level implementation, compare results functional level description its implementation. Whenever an error detected, logic diagnosis can used provide useful information designers. shown that certain types combinational detected allocated by LOVERD efficiently.