SRAM cell for high noise margin and soft errors tolerance in nanoscale technology
作者：
DOI: 10.1109/COMMANTEL.2014.6825586
关键词: Embedded system 、 Margin (machine learning) 、 CMOS 、 Overhead (computing) 、 Static random-access memory 、 Transistor 、 Noise margin 、 Computer science 、 Electronic engineering 、 Topology (electrical circuits) 、 Reliability (semiconductor)
摘要: In this paper, we present various techniques used to improve SRAM stability and their trade-offs conventional 6T-SRAM. The performance of these structures is analyzed in terms reliability, speed, size, leakage power by using HSPICE simulator 90nm 32nm CMOS processes. technology, 8T cell shows an improvement 2.1X read margin area penalty over 24% compared 6T cell. For process, the 9.78X overhead 29%. On other hand, also allows different words be written simultaneously while taking advantages LS-layout topology Therefore, most suited replace structure next advanced addition, study that a 12T with high less sensitive soft errors totally feasible.
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