A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
作者： Shah M. Jahinuzzaman , David J. Rennie , Manoj Sachdev
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摘要: We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for sensing. The exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional tolerant 12 T DICE cell. When compared to conventional 6 cell, proposed similar as at half supply voltage, thus significantly saving power. In addition, 98% lower rate accelerated neutron radiation tests carried out TRIUMF on 32-kb implemented 90-nm CMOS technology.
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