A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages

摘要: A full-custom VLSI chip demonstrates an arithmetic implementation for computing the mantissa of a 54-b (floating-point double-precision) division operation in 45 ns to 160 ns, depending on data. The design uses self-timing avoid need partition logic into clock cycles and high-speed clocks. Self-timing allows circuits iterate with no overhead over pure combinational delays. It also greater-efficiency symmetric overlapped execution SRT stages because dynamic path ordering. has several other performance enhancements, their effects are discussed. total effect all enhancements provides factor two increase due architectural improvements straightforward approach. >