Method and apparatus for adaptive verification of circuit designs

摘要: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of device under test (DUT). HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, provides facility comprised three main stages: i) Coverage Definitions, ii) Instantiation and Triggering iii) Feedback. A coverage definition is very similar an class definition, but does not contain methods or variables. Instead, basic purpose declare “monitor bins” in terms state variable. Essentially, each monitor bin declaration has unique name associated with particular behavior variable used record variable's behavior. produces instance. Two key instantiation parameters are: actual that be monitored by instance trigger expression determines when monitored. Instantiating means concurrent, non-terminating, “coverage process” also forked off. “foreground” thread control off process may continue operate subject DUT stimuli. DUT's responses such stimuli stored as data same foreground subjecting can query resulting instance's data. This ability make possible “closed loop” testing since subsequently alter further generated for based upon results its query.