作者: S.W. White , P.D. Hester , J.W. Kemp , G.J. McWilliams
DOI: 10.1109/40.238004
关键词: Orthogonal instruction set 、 Instruction register 、 Addressing mode 、 Operating system 、 Minimal instruction set computer 、 Computer science 、 Instruction cycle 、 Cycles per instruction 、 Central processing unit 、 Reduced instruction set computing 、 Computer hardware 、 Application-specific instruction-set processor 、 Instruction path length 、 DEC Alpha 、 Clock rate 、 Instruction set
摘要: For part I, see ibid., vol.13, no.4, p.8-16 (1993). Two processors that compete in the workstation/server markets are compared. The 62.5-MHz IBM RISC System/6000 Model 580 exemplifies a moderate clock rate design. 133-1200-MHz DEC Alpha processor represents an aggressive performance implications of memory subsystems and effect instruction sets on path length described. It is shown measurements many systems support initial claim cycle time not sufficient to determine performance. >