How does processor MHz relate to end-user performance? II. Memory subsystem and instruction set

作者: S.W. White , P.D. Hester , J.W. Kemp , G.J. McWilliams

DOI: 10.1109/40.238004

关键词: Orthogonal instruction setInstruction registerAddressing modeOperating systemMinimal instruction set computerComputer scienceInstruction cycleCycles per instructionCentral processing unitReduced instruction set computingComputer hardwareApplication-specific instruction-set processorInstruction path lengthDEC AlphaClock rateInstruction set

摘要: For part I, see ibid., vol.13, no.4, p.8-16 (1993). Two processors that compete in the workstation/server markets are compared. The 62.5-MHz IBM RISC System/6000 Model 580 exemplifies a moderate clock rate design. 133-1200-MHz DEC Alpha processor represents an aggressive performance implications of memory subsystems and effect instruction sets on path length described. It is shown measurements many systems support initial claim cycle time not sufficient to determine performance. >

参考文章(1)
R.L. Sites, R.T. Witek, Alpha architecture and first implementation Digest of Papers COMPCON Spring 1992. pp. 214- ,(1992) , 10.1109/CMPCON.1992.186711