Statistical leakage estimation for DRAM circuits

摘要: Power consumption has become a key constraint in VLSI designs. Leakage current becomes dominant part of the total power dissipation. In addition, with technology scaling into sub-50nm regime, one main design challenges presence process variations is to cope uncertainties timing and power. Since leakage highly dominated by variations, statistical estimation essential for robust circuit design. Process can be monitored analyzing test element group (TEG). DRAM down mode ICC2P parameter. To obtain current, we need long circuit-level simulation an accurate transistor modeling. Therefore, solve this problem, practical framework which based on switch-level standby vector dependent analysis. paper, proposed TEG analysis methodology estimate at mode. Experiments benchmark circuits demonstrate that estimated results our are very compared measurement data from industrial fabrication.