Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)

作者: Anantha Chandrakasan , Siva G. Narendra

DOI:

关键词:

摘要:

参考文章(10)
D. A. Muller, T. Sorsch, S. Moccio, F. H. Baumann, K. Evans-Lutterodt, G. Timp, The electronic structure at the atomic scale of ultrathin gate oxides Nature. ,vol. 399, pp. 758- 761 ,(1999) , 10.1038/21602
Max Schulz, The end of the road for silicon Nature. ,vol. 399, pp. 729- 730 ,(1999) , 10.1038/21526
Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, Low-Power CMOS Digital Design IEICE Transactions on Electronics. pp. 371- 382 ,(1992)
B. Hoeneisen, C.A. Mead, Fundamental limitations in microelectronics—I. MOS technology Solid-state Electronics. ,vol. 15, pp. 819- 829 ,(1972) , 10.1016/0038-1101(72)90103-7
G.E. Moore, Cramming More Components Onto Integrated Circuits Proceedings of the IEEE. ,vol. 86, pp. 56- 59 ,(1998) , 10.1109/JPROC.1998.658762
Robert Chau, Boyan Boyanov, Brian Doyle, Mark Doczy, Suman Datta, Scott Hareland, Ben Jin, Jack Kavalieros, Matthew Metz, Silicon nano-transistors for logic applications Physica E-low-dimensional Systems & Nanostructures. ,vol. 19, pp. 1- 5 ,(2003) , 10.1016/S1386-9477(03)00284-4
Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester, Analysis and minimization techniques for total leakage considering gate oxide leakage Proceedings of the 40th conference on Design automation - DAC '03. pp. 175- 180 ,(2003) , 10.1145/775832.775878
T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakurai, A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme international solid-state circuits conference. ,vol. 31, pp. 1770- 1779 ,(1996) , 10.1109/JSSC.1996.542322
A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01. pp. 207- 212 ,(2001) , 10.1145/383082.383135
Jong-Ho Lee, G. Taraschi, Andy Wei, T.A. Langdo, E.A. Fitzgerald, D.A. Antoniadis, Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy international electron devices meeting. pp. 71- 74 ,(1999) , 10.1109/IEDM.1999.823849