作者: Javier Castro , Pilar Parra , Antonio J. Acosta
DOI: 10.1007/978-3-642-11802-9_12
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摘要: Leakage power dissipation has become a critical issue in advanced pro cess technologies. The use of techniques to reduce leakage consumption with negligible degradation performances is needed for current and next tech nologies. Power gating an effective technique leakage, taking advantage the transistor stacking effect. However, restoration from standby mode power-gated circuits usually introduces large amount switching noise on supply ground networks, that may affect normal operation connected same polarizations. This paper analyzes generated wake-up phase by several power-gat ing techniques, their influence time. best results are redistribute flowing through Vdd Gnd nodes during transition. Simulation obtained basic digital cells 90 nm technology show variation two noise, while maintaining time saving.