Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression

摘要: This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in wakeup are controlled in fine granularity run time, shortening the transition time between sleep active states is strongly required. In particular, essential because it affects execution hence does performance. However, this requirement makes suppression of ground-bounce more difficult. We propose novel technique to skew timings local domains suppress ground bounce. Delay buffers driving switches skewed buffer tree by selectively downsizing them. designed MIPS R3000 based CPU core 90nm CMOS technology applied our internal function units. Simulation results showed that reduces rush current 47% over case turn-on simultaneously. resulted suppressing bounce 53mV with 3.3ns time. from running benchmark programs total dissipation units was reduced up 15% at 25°C 62% 100°C. Effectiveness savings discussed viewpoint temperature-dependent break-even points consecutive idle program.