Segmented Virtual Ground Architecture for Low-Power Embedded SRAM
作者： Mohammad Sharifkhani , Manoj Sachdev
DOI: 10.1109/TVLSI.2007.893584
关键词:
摘要: A new scheme to reduce the power consumption of static random access memories is presented. It shown that using segmented virtual grounding (SVGND), it possible both dynamic and consumption. The leakage cells reduced by reducing voltage drop over a cell. dissipation also eliminating due discharge nondesired neighboring bitlines. effectiveness this compared recently reported low-power schemes. unlike those schemes, SVGND can accommodate multiple words in one row; significant improvement soft error rate tolerance
sci-hub.se 参考文章(14)
Anantha Chandrakasan, Siva G. Narendra, Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems) Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems). ,(2005)
Nobutaro Shibata, A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's IEICE Transactions on Electronics. ,vol. 80, pp. 1598- 1607 ,(1997)
Anantha P. Chandrakasan, Siva G. Narendra, Leakage in Nanometer CMOS Technologies Leakage in Nanometer CMOS Technologies 1st. pp. 307- 307 ,(2010)
Byung-Do Yang, Lee-Sup Kim, A low-power SRAM using hierarchical bit line and local sense amplifiers IEEE Journal of Solid-state Circuits. ,vol. 40, pp. 1366- 1376 ,(2005) , 10.1109/JSSC.2005.848032
Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, Review and future prospects of low-voltage RAM circuits Ibm Journal of Research and Development. ,vol. 47, pp. 525- 552 ,(2003) , 10.1147/RD.475.0525
B.S. Amrutur, M.A. Horowitz, A replica technique for wordline and sense control in low-power SRAM's IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 1208- 1219 ,(1998) , 10.1109/4.705359
M. Matsumiya, S. Kawashima, M. Sakata, M. Ookura, T. Miyabo, T. Koga, K. Itabashi, K. Mizutani, H. Shimada, N. Suzuki, A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture IEEE Journal of Solid-state Circuits. ,vol. 27, pp. 1497- 1503 ,(1992) , 10.1109/4.165328
H.J.M. Veendrick, The behaviour of flip-flops used as synchronizers and prediction of their failure rate IEEE Journal of Solid-state Circuits. ,vol. 15, pp. 169- 176 ,(1980) , 10.1109/JSSC.1980.1051359
K.W. Mai, T. Mori, B.S. Amrutur, R. Ho, B. Wilburn, M.A. Horowitz, I. Fukushi, T. Izawa, S. Mitarai, Low-power SRAM design using half-swing pulse-mode techniques IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 1659- 1671 ,(1998) , 10.1109/4.726555
K. Itoh, K. Sasaki, Y. Nakagome, Trends in low-power RAM circuit technologies Proceedings of the IEEE. ,vol. 83, pp. 524- 543 ,(1995) , 10.1109/5.371965