Deep submicron implementation of gating transistor power saving technique for power optimized code book SRAM
作者： Madan Mali , M.S. Sutaone , Mangesh Bhalerao , Shital Tak
DOI: 10.1109/ICIEA.2009.5138681
关键词: Static random-access memory 、 Electrical engineering 、 Dram 、 Transistor 、 Voltage 、 Electronic engineering 、 Access time 、 Dissipation 、 Engineering 、 Spice 、 CMOS
摘要: Embedded SRAM has plentiful of applications in signal processing as an on chip RAM. The prime benefit is its speed compared to DRAM. threat dissipation targeted here. This code book vector quantizers for image compression reduced. measured at various combinations supply voltage and precharge array. optimized combination minimum computed. These voltages are 620mV 300mV respectively. Additionally the power also reduced by 7% 13% additional gating transistor different levels. access time 2 ns. reliability improved adding redundant rows columns. CMOS layout done 0.25µm technology array size 256×8 16 such arrays.
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