作者: Rajendra M. Rewatkar , Sajay L. Badjate
关键词: Full custom 、 Signal processing 、 Process variation 、 Electronic circuit 、 Computer science 、 Logic synthesis 、 Digital signal processing 、 Very-large-scale integration 、 Electronic engineering 、 Circuit design
摘要: A Paper presents new scaling techniques of multirate digital signal processing system. It has been done with 0.45 nm synopsis tool and AMI 0.6 um TSMC 0.25 technology at different voltages. All basic Multirate modules are design using Active-HDL QUARTUS-II platform then it is synthesized on FPGA Alter a DE-1 kit. For the optimization coefficient transistor level circuits simulated cadence platform. The circuit verified implemented successfully for low power high speed. proposed methodology provides systematic speed operation supply. Authors have up sampler, down interpolator decimator which given full custom topology level. observations parameters area, taken voltages technology. Finally, implementation report presented.