A VLSI architecture for a universal high-speed multirate FIR digital filter with selectable power-of-two decimation/interpolation ratios
作者： H. Samueli , T.-J. Lin
DOI: 10.1109/ICASSP.1991.150697
关键词:
摘要: A universal architecture for decimation/interpolation digital filtering applications is proposed custom VLSI implementation to accommodate real-time signal processing at throughput rates in excess of 100 MHz. The main innovation this that it allows a single chip selectively perform decimation or interpolation with selectable conversion ratios 2/sup 1/,2/sup 2/,. . .2/sup N/. key feature the decimate/interpolate-by-two half-band filter used as computational engine, and output samples are simply recycled through same after each stage further filtering. delicate timing allocation scheme be shared among plays critical role allowing have still >
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