Compiler Reduction of Invalidation Traffic in Virtual Shared Memory Systems

作者: M. F. P. O'Boyle , R. W. Ford , A. P. Nisbet

DOI: 10.1007/3-540-61626-8_58

关键词: Memory orderingDistributed memoryMemory managementMemory modelSPMDDistributed shared memoryExtended memoryExecution modelData diffusion machineCache coherenceUniform memory accessShared memoryMemory footprintComputer scienceInterleaved memoryParallel computingCompilerOverlayMemory mapVirtual memory

摘要: This paper presents new compiler analysis for the elimination of invalidation traffic in virtual shared memory, using a hybrid distributed coherence scheme. The and acknowledgement messages are removed; this reduces both network latency write fault. It aggressively exploits SPMD execution model uses array section to accurately determine only those instances when is necessary, thus avoiding additional read misses previous schemes. Equations determining precisely what data should be invalidated presented translated into form amenable analysis. Preliminary experimental results on 30 node prototype architecture demonstrate performance attainable

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