System-level Pareto frontiers for on-chip thermoelectric coolers

摘要: The continuous rise in heat dissipation of integrated circuits necessitates advanced thermal solutions to ensure system reliability and efficiency. Thermoelectric coolers are among the most promising techniques for dealing with localized on-chip hot spots. This study focuses on establishing a holistic optimization methodology such thermoelectric coolers, which element’s thickness electrical current optimized minimize source temperature respect ambient, when parasitic effects considered. It is found that element given architecture, “heat flux vs. difference” Pareto frontier curve obtained, indicating there an optimum corresponding maximize achievable reduction while removing particular flux. also provides possible level ΔT’s can be achieved range fluxes, defining upper limits cooling architecture. In this study, use was made extensive analytical model, verified using commercially available finite analysis software. Through process, 3 pairs master curves were generated, then used compose any Finally, case performed provide in-depth demonstration procedure example application.