Parallel-pipeline 8/spl times/8 forward 2-D ICT processor chip for image coding

摘要: The Integer Cosine Transform (ICT) presents a performance close to Discrete (DCT) with reduced computational complexity. ICT kernel is integer-based, so computation only requires adding and shifting operations. This work parallel-pipelined architecture of an 8/spl times/8 forward two-dimensional (2-D) ICT(10,9,6,2,3,1) processor for image encoding. A fully pipelined row-column decomposition method based on two one-dimensional (1-D) ICTs transpose buffer D-type flip-flops used. main characteristics 1-D are high throughput, parallel processing, internal storage, 100% efficiency in elements. arithmetic units distributed made up adders/subtractors operating at half the frequency input data rate. In this transform, truncation rounding errors introduced final normalization stage. coefficient word length 18-bit (13-bit effective) has been established using requirements IEEE standard 1180-1990 as reference. implemented cell design methodology 0.35-/spl mu/m CMOS technology, measures 9.3 mm/sup 2/, contains 12.4 k gates. maximum 300 MHz latency 214 cycles (260 normalization).