A design of 2-D DCT/IDCT for real-time video applications
作者： Ig-Kyun Kim , Jin-Jong Cha , Han-Jin Cho
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摘要: In this paper, we present the implementation of 2-D DCT/IDCT that is capable processing an 8/spl times/8 pixel block and satisfies accuracy specification ITU-T. This circuit was designed for real-time 33 MHz sample rate video data. It uses row-column decomposition to implement a two dimensional transform. Distributed arithmetic combined with bit-serial bit-parallel structures used required vector inner product concurrently. The resultant only memory shift registers, adders. No multipliers are required. has been laid out using 0.5 /spl mu/m CMOS technology, contains 10000 gates approximately 64/spl times/16 bit memory.
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