TCAD: a 27 MHz 8*8 discrete cosine transform chip

摘要: The circuit performs two-dimensional forward and inverse discrete cosine transform (DCT) on 8*8 blocks of data. Its implementation is based the row-column decomposition scheme. A memory look-up approach combined with bit-serial structures used to compute each one-dimensional DCT. register-based transposition stage maintains serial representation data after first transform. This 50000-transistor only uses read-only memories, registers, adders. pipeline architecture a very regular layout lead high-speed performances up digital TV rates. 32-pin version accepts 9-bit pixel input produces 12-bit coefficients in mode vice-versa for DCT mode. area 26 mm/sup 2/ 1.2- mu m CMOS technology. >