High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

作者: G. A. Ruiz , J. A. Michell , A. Burón

DOI: 10.1007/S11265-006-9764-7

关键词: CMOSChipDiscrete cosine transformImage compressionComputer scienceStandard cellImage processingComputer hardwareParallel computingCodecTranspose

摘要: This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses fully pipelined row---column decomposition method based on two 1-D DCT processors transpose buffer D-type flip-flops with double serial input/output data-flow. The proposed architecture allows the main elements arithmetic units to operate in parallel at half frequency of input rate. characteristics are: throughput, processing, reduced internal storage, maximum efficiency computational elements. has been implemented using standard cell design methodology 0.35 ?m CMOS technology. measures 6.25 mm2 (the core is 3 mm2) contains total 11.7 k gates. 300 MHz latency 172 cycles 178 IDCT. computing time block close 580 ns. designed meets demands IEEE Std. 1,180---1,990 used different codecs. good performance speed hardware cost indicate that this suitable HDTV applications.

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