A 100 MHz 2-D 8/spl times/8 DCT/IDCT processor for HDTV applications
作者： A. Madisetti , A.N. Willson
DOI: 10.1109/76.388064
关键词: 12-bit 、 Real-time computing 、 Integrated circuit layout 、 Integrated circuit 、 Transform coding 、 Pixel 、 Computer science 、 High-definition television 、 CMOS 、 Signal processing 、 Computer hardware
摘要: This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing HDTV signals. The processor operates on 8/spl times/8 blocks. Inputs include blocked pixels that are scanned one pixel at time, and external control signals forward or inverse modes operation. Input have precision 9-b DCT 12-b IDCT. layout has been generated with 0.8 /spl mu/m library using Mentor Graphics GDT tools measures under 10 mm/sup 2/. Critical path simulation indicates maximum input sample rate 100 MHz. >
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